PnR Lead Engineer -San Jose CA

Job Description

• Responsible for leading the physical design and place & route (PnR) activities for clients' semiconductor designs • Work closely with cross-functional teams to ensure successful implementation of complex ASIC and FPGA designs • Signoff activities including Static-IR/Dynamic-IR/Power-EM/Signal-EM Analysis using RHSC • Implementation tasks like Synthesis, CDC concepts and analysis, netlist verification, etc. • STA activities with good timing concepts and understanding of timing reports • Must have experience in tapped out multiple projects and closed complete Signoff • Help with Block IR closure as well

Qualifications

• 8 to 12 years of relevant experience in physical design and place & route (PnR) • Expert in TCL or Python scripting • Experience with industry-standard EDA tools such as Cadence Innovus or Synopsys ICC • Strong proficiency in floorplanning, power planning, and routing techniques • Knowledge of clock tree synthesis and optimization • Experience with static timing analysis and timing closure • Understanding of design for manufacturability (DFM) and design for testability (DFT) techniques • Excellent problem-solving and analytical skills • Good communication and collaboration abilities • BS or MS degree in Electrical Engineering or a related field

Benefits

• Competitive salary based on experience • Health insurance • Retirement plan contribution matching • Paid time off • Professional development opportunities